The present invention relates generally to routing for devices with different pitch, and more particularly to routing of a core embedded in a programmable logic device where the core comprises a different pitch than the programmable logic device.
Programmable logic devices exist as a well-known type of integrated circuit that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic devices, called a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, and the like, though other types of memory may be used. The collective states of the individual memory cells then determine the function of the FPGA.
A recent development in FPGA technology involves providing FPGAs comprising a plurality of what are known as xe2x80x9cstandard cells.xe2x80x9d These xe2x80x9cstandard cellsxe2x80x9d are provided inside an FPGA as functional blocks and have a set height. Notably, the term xe2x80x9cstandard cellxe2x80x9d is not to imply that any standard, de facto or otherwise, exists, as standard cell size may vary from company to company. So, for example, logic blocks, such as a flip-flop, a NAND gate, and an inverter, among other well-known logic circuits, each will lay out with a same height, but may have different lengths. This height is conventionally dependent on pitch of a company""s integrated circuit process for one or more interconnect or metal layers. A standard cell may be made up of several logic blocks, each with a same height, but possibly with different lengths. Thus, each standard cell will have a same height but may have varying lengths. Standard cells may be assembled for providing interconnectivity logic or xe2x80x9cglue logic.xe2x80x9d Thus, an FPGA may be connected to an embedded device to carry out complex tasks.
However, an embedded device or core may not have the same layout pitch as an FPGA. Moreover, FPGA exclusive routing over an embedded core further complicates routing to an embedded core. A placement and routing database used by a routing program creates routing for connecting an FPGA to an embedded core. However, non-equivalent pitch between such an FPGA and embedded core causes design rule violations. These design rule violations heretofore were addressed by manual re-routing. However, checking a design for such violations and manually re-routing can delay production by one or more months depending on complexity and number of connections between the FPGA and embedded core.
Accordingly, it would be desirable and useful to provide a layout rules for implementation in a placement and routing database that would reduce design rule violations owing to differences in pitch between an FPGA and an embedded core.
An aspect of the present invention is a method for configuring a routing program for routing connections between an integrated circuit device and an embedded core. More particularly, a first horizontal pitch and a first vertical pitch is obtained for one of the integrated circuit device and the embedded core, and a second horizontal pitch and a second vertical pitch is obtained for the other of the integrated circuit device and the embedded core, where the first vertical pitch and the second vertical pitch are not equal. A first connection layer input, including, but not limited to, the first vertical pitch and a horizontal direction, is provided to the routing program, and a second connection layer input, including, but not limited to, the second horizontal pitch and a vertical direction, is provided to the routing program.
An aspect of the present invention is an integrated circuit device comprising a first device coupled to a second device. The first device comprises a first horizontal pitch and a first vertical pitch. The second device comprises a second horizontal pitch and a second vertical pitch. At least one interconnect layer is for coupling the first device and the second device. The interconnect layer comprises a set of pitches selected from: (i) the first vertical pitch and the second horizontal pitch, and (ii) the first horizontal pitch and the second vertical pitch.